Implementation of Wallace Tree Multiplier in FFT
Paper ID:
IJSDIP_2016_VOLUME 4_ISSUE 1_37-41
Author's Name:
Dr. Rakhi Thakur
Volume:
4
Issue:
Issue 1
Year:
2016
Pages:
37-41
Abstract
A scalable architecture for pipelined and iterative Wallace tree multipliers is presented. For netlist-only multipliers, minimal latency and number of pipeline stages are achieved through a delay-driven design scheme. The architecture can be modified to a tree-of- Wallace-trees structure for regular layout, at the expense of latency. The achievable minimal cycle time equals the delay through two full adder cells, plus the setup time and delay through a register. The ―elemental‖ Wallace trees in this architecture can also be used in itemtive structures that provide a variety ofdelay/gate-count tradeoffs.
Keywords
Wallace tree multiplier, FFT