On Chip CMOS Microstrip Antenna Design for WSN Application: A Review
Abstract
In order to create a small front-end receiver for 5G communication systems, this paper explores the design factors and difficulties of integrating on-chip antennas in nanoscale CMOS technology at millimetre-wave (mm-wave). In the face of strict metal density regulations and other back-end-of-the-line (BEoL) difficulties of nanoscale technology, a monolithic on-chip antenna is created and optimised. The radiation efficiency and power gain of the suggested antenna structure are increased by 37.3% and 9.8 dB, respectively, while the silicon area is reduced by up to 30% compared to earlier works, further utilising ground metallization on a PCB board serving as a reflector. In order to prevent extra matching or interconnect losses, the antenna is directly matched to a 2-stage LNA in a manner that creates an active integrated antenna (AIA). A double-balanced folded Gilbert cell mixer comes after the LNA and generates a lower intermediate frequency (IF), which eliminates the need for probing during readings.
Keywords
Chip CMOS, Microstrip Antenna Design, WSN Application, 5G Communication Systems.