IJSDIP | International Journal of System Design & Info Processing

A Fast and Energy-Efficient Rounding-Based Multiplier Architecture (RoBA) for DSP Applications

Paper ID:

IJSDIP_2025_VOLUME 13_ISSUE 4_8-19

Author's Name:

Akkali Sowmya, D Satheesh

Volume:

Issue:

Issue 4

Year:

2025

Pages:

8-19

Abstract

This research presents a novel rounding-based approximate multiplier architecture (RoBA) that achieves a compelling trade-off between computational accuracy, high-speed performance, and energy efficiency, making it well-suited for modern digital signal processing (DSP) and image processing applications. The key innovation lies in the strategic rounding of operands to the nearest power of two, which simplifies multiplication by reducing it to a sequence of shift and add operations. This approach effectively bypasses the most computation-intensive stages of conventional multipliers, leading to reduced propagation delay, lower dynamic power consumption, and minimized hardware complexity. Despite introducing a bounded approximation error, the proposed design demonstrates significant improvements in throughput and energy savings, particularly under tight resource constraints. The architecture supports both signed and unsigned multiplication, and is realized in three hardware configurations: one for unsigned operations and two for signed operations, with one configuration specifically optimized for enhanced accuracy in negative value computations. Comprehensive evaluations are performed using industry-standard synthesis tools and benchmark circuits to assess key performance metrics, including area utilization, power dissipation, critical path delay, and error rate. To validate real-world applicability, the proposed multiplier is deployed in two representative image processing pipelines—image smoothing (e.g., Gaussian blur, mean filtering) and image sharpening (e.g., unsharp masking)—which heavily rely on multiply-accumulate operations. Simulation results confirm that the approximate multiplier maintains acceptable visual fidelity while significantly reducing computational and energy overhead. When compared with traditional accurate multipliers and state-of-the-art approximate designs, the proposed RoBA architecture consistently delivers superior results in terms of energy efficiency and speed. Its low hardware footprint, high throughput, and tolerance to minimal error make it an ideal candidate for low-power embedded systems, portable devices, and real-time DSP applications where energy efficiency is prioritized over exact arithmetic precision.

Keywords

Approximate Multiplier, Rounding-Based Architecture, Low-Power Design, Digital Signal Processing, Image Processing

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DOI: https://doi.org/10.64971/j.cph.ijsdip.v13.i4.2.2025