Paper ID:
IJSDIP_2025_VOLUME 13_ISSUE 4_29-38
Author's Name:
Pentam Vasanth Kumar, Immidisetty V. Prakash
Volume:
13
Issue:
Issue 4
Year:
2025
Pages:
29-38
Abstract
High-throughput Finite Impulse Response (FIR) filters are basic building blocks in many fields including digital signal processing (DSP), communications, image and video addition processing, biomedical instrumentation, and control systems. They have deterministic response, are inherently stable, and have linear phase, which makes them very attractive for real-time applications where accuracy and computation speed are of utmost importance.
In this paper, we investigate the design of FIR filters on Field Programmable Gate Arrays (FPGAs) using systolic array architectures. The proposed design method combines multi-channel processing with symmetric coefficient optimization so as to realizing high computational rate silicon efficient implementation.
The heart of this architecture is the systolic FIR filter, which is known for its modularity, synchronization, and regularity—essential aspects that make the design scalable and structured for VLSI. The systolic array's distributed processing also has the effect of making the data flow rhythmically through a chain of processing elements, which greatly reduces routing complexity and enhances timing closure for FPGA implementations.
Perhaps the best strengths of this architecture reside in the embedded dsp blocks of the newer FPGAs. These units are strongly optimized for the critical Multiply-Accumulate (MAC) operations part of DSP and play a central role in implementing low-latency pipelines for high-throughput filtering. Since most of the logic is consumed to make arithmetic operation (especially multiply) and since this architecture allows to offload hard arithmetic calculations to dedicated hardware elements, lowest usage of logic along with highest performance can be achieved. Apart from this, a common characteristic in linear-phase FIR filters is exploited in FIR filter design, that is coefficient symmetry. Applying symmetry, the number of multipliers can be reduced to half, which will result in a considerable saving of hardware. As a result, the symmetry also reduces the strength of memory access, and, therefore, power/area are further optimized.
The pipeline structure of our proposed systolic architecture allows all processes to be executed in parallel, resulting in increased throughput and reduced critical path delay. Pipelining has additional advantages for the FPGA since pipelines help mitigate the effects of long logic chains on the clock frequency and reliability.
Overall, the systolic structure, DSP block usage, coefficient symmetry and pipelining technique allow for a very efficient FIR filter realization. Our proposed core achieves excellent performance in throughput, area and power efficiency, and is thus very applicable to real-time signal processing applications mapped on reconfigurable hardware.
Finally, an Implementation of the proposed systolic FIR filter design on FPGAs is a promising option for high-throughput signal-processing applications. This design achieves the best balance in throughput, hardware resource consumption and flexibility, which proves the significance of FPGA-based DSP systems in the space of modern embedded and real-time computing applications.
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