IJSDIP | International Journal of System Design & Info Processing

Fault Space Transformation-Based Design Methodology for Robust Parallel Filtering Systems

Paper ID:

IJSDIP_2025_VOLUME 13_ISSUE 4_39-44

Author's Name:

Botla Sujatha, Dr. V. Sapthagiri

Volume:

Issue:

Issue 4

Year:

2025

Pages:

39-44

Abstract

The complexity of today’s communication and signal processing systems has increased, and so has the number of functional blocks, such as digital filters. Many of these blocks are in parallel to perform the same operations on different data streams. This upsurge of parallelism brings up utmost reliability concerns which require designing fault-tolerant architectures. A fault-tolerance technique based on error correction coding has recently been proposed that represents every filter as a data bit, with other redundant filters acting as parity check bits to detect and recover from faults. In this thesis, that idea is further developed by means of a general framework for using coding to increase the fault tolerance of parallel filters. Unlike classical bit-level coding, the method takes advantage of the fact that the inputs and the outputs of the filters are numbers to provide an efficient and scalable fault protection scheme. In particular, it makes the number of needed redundant filters independent from the number of parallel filters, diminishing the implementation complexity. The proposed technique is fully developed and demonstrated by means of two practical/examples. In addition, its potential in error protection and the related hardware overhead are evaluated by a realisation on a field programmable gate array (FPGA) platform.

Keywords

Fault Space, Verilog, Parallel Filter, Vivado, Modelsim

References

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DOI: https://doi.org/10.64971/j.cph.ijsdip.v13.i4.5.2025