Paper ID:
IJSDIP_2025_VOLUME 13_ISSUE 2_61-68
Author's Name:
Senthil Kumar M, Sapthagiri Vienala
Volume:
13
Issue:
Issue 2
Year:
2025
Pages:
61-68
Abstract
High-throughput Finite Impulse Response (FIR) filters are essential in DSP, communications, biomedical, and control systems due to their stability, deterministic response, and linear-phase characteristics, making them ideal for real-time applications requiring high accuracy and speed.
This paper presents an optimized FPGA implementation of symmetric systolic FIR filters using a multi-channel processing architecture. The proposed design leverages the regularity, modularity, and synchronization of systolic arrays to achieve scalable and structured VLSI implementation. Data flows rhythmically through processing elements, minimizing routing complexity and improving timing closure. By exploiting coefficient symmetry, the design reduces the number of multipliers by half, resulting in lower logic utilization and power consumption. The integration of embedded DSP blocks within modern FPGAs enhances Multiply–Accumulate (MAC) performance, supporting high-speed and low-latency operation. The pipelined systolic structure enables concurrent processing, increasing throughput and reducing critical path delay. Together, systolic design, DSP block optimization, and coefficient symmetry yield a hardware-efficient FIR filter architecture that achieves excellent trade-offs in area, power, and performance, making it highly suitable for real-time FPGA-based signal processing applications.
References
[1] Jiang, Honglan, et al. "A high-performance and energy-efficient FIR adaptive filter using approximate distributed arithmetic circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 66.1 (2018): 313-326.
[2] Praveen Sundar, P. V., et al. "Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture." International Journal of Speech Technology 23.2 (2020): 287-296.
[3] Venkatachalam, Suganthi, et al. "Design and analysis of area and power efficient approximate booth multipliers." IEEE Transactions on Computers 68.11 (2019): 1697-1703.
[4] Vahdat, Shaghayegh, et al. "TOSAM: An energy-efficient truncation-and rounding-based scalable approximate multiplier." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27.5 (2019): 1161-1173.
[5] Cai, Fuxi, et al. "Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks." Nature Electronics 3.7 (2020): 409-418.
[6] Ying, Zhoufeng, et al. "Electronic-photonic arithmetic logic unit for high-speed computing." Nature communications 11.1 (2020): 1-9.
[7] Leon, Vasileios, et al. "Walking through the energy-error Pareto frontier of approximate multipliers." IEEE Micro 38.4 (2018): 40-49.
[8] Soares, Leonardo Bandeira, et al. "Design methodology to explore hybrid approximate adders for energy-efficient image and video processing accelerators." IEEE Transactions on Circuits and Systems I: Regular Papers 66.6 (2019): 2137-2150.
[9] Ankit, Aayush, et al. "Panther: A programmable architecture for neural network training harnessing energy-efficient reram." IEEE Transactions on Computers 69.8 (2020): 1128-1142.
[10] Bashar, Manijeh, et al. "Energy efficiency of the cell-free massive MIMO uplink with optimal uniform quantization." IEEE Transactions on Green Communications and Networking 3.4 (2019): 971-987.
[11] Akhter, Shamim, Satyendra Kumar, and Divya Bareja. "Design and analysis of distributed arithmetic based FIR filter." 2018 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN). IEEE, 2018.
[12] Narendiran, S., and E. P. Jayakumar. "An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter." 2021 Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2021.
[13] Radhakrishnan, S., et al. "Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier." 2020 5th IEEE International Conference on Emerging Electronics (ICEE). IEEE, 2020.
[14] Mahalakshmi, R., and T. Sasilatha. "An Improved Digital FIR Filter Design Using Fast FIR Algorithm and Modified Carry Save Addition." National Academy Science Letters 41.3 (2018): 147-150.
[15] Thanmai, T., and J. V. R. Ravindra. "High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier." 2020 International Conference on Applied Electronics (AE). IEEE, 2020.
[16] Chinnapparaj, S. Certain investigations on design and implementation of digital fir filter using low power and high speed multipliers. Diss. ANNA UNIVERSITY CHENNAI, 2019.
[17] Datta, Debarshi, and Himadri Sekhar Dutta. "Efficient FPGA Implementation of FIR Filter Using Distributed Arithmetic." Energy Systems, Drives and Automations. Springer, Singapore, 2020. 151-160.
[18] Ramamoorthy, Prabhu, and Viswanathan Nallasamy. "Review of Multiplierless Fir Filter Design Based On Graph Based Optimization." 2018 Conference on Emerging Devices and Smart Systems (ICEDSS). IEEE, 2018.
[19] Narendran, S., and B. T. Geetha. "Performance Analysis of Parallel FIR Digital Filter Based on Even Symmetric Fast FIR Algorithm using Different Adders." 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2021.
[20] Kumar, Prashant, et al. "High-throughput, area-efficient architecture of 2-D block FIR filter using distributed arithmetic algorithm." Circuits, systems, and signal processing 38.3 (2019): 1099-1113.
