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A Novel Low-Leakage SRAM Cell Architecture for Ultra-Low-Power VLSI Systems

Paper ID:
IJSDIP_2025_VOLUME 13_ISSUE 3_47-56
Author's Name:
Ponugupati Kiran Kumar, Dr. B. Prabhakar, Sarita Chagantipati
Volume:
13
Issue:
Issue 3
Year:
2025
Pages:
47-56

Abstract

Static Random-Access Memory (SRAM) represents a major contributor to on-chip power consumption in modern VLSI systems, particularly in energy-constrained platforms such as IoT nodes, biomedical implants, wearables, and edge-AI accelerators. Conventional 6T SRAM cells exhibit high leakage, degraded stability at low voltages, and increased sensitivity to process variations. This paper proposes a novel low-leakage SRAM cell architecture optimized for ultra-low-power operation. The design integrates virtual-ground power gating, dual-threshold transistor assignment, and adaptive body biasing, achieving substantial reduction in leakage without sacrificing performance. A read-decoupled write-assist technique further enhances Static Noise Margin (SNM) and writability under near-threshold and sub-threshold operation. Simulations in 45 nm and 32 nm CMOS demonstrate 65–80% lower leakage, 40% higher retention stability, and 32% reduced write energy compared with 6T/8T cells. Monte Carlo analysis validates robustness across process, voltage, and temperature (PVT) variations, making the proposed architecture highly suitable for next-generation low-power VLSI systems.

Keywords

Low-leakage SRAM, Ultra-low-power VLSI, Sub-threshold operation, 6T SRAM, Read-decoupled architecture, Power gating, Leakage reduction, Static Noise Margin (SNM), Near-threshold computing, IoT memory design.

References

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DOI: https://doi.org/10.64971/j.cph.ijsdip.v13.i3.7.2025