IJSDIP | International Journal of System Design & Info Processing

HIGH-SPEED REAL-TIME SIGNAL PROCESSING ON FPGAS USING MEMORY-AWARE ARCHITECTURE OPTIMIZATION

Paper ID:

IJSDIP_2024_VOLUME 12_ISSUE 3_101-110

Author's Name:

Chetti. Venkateswarlu, Dr. Tipparti. Anil Kumar

Volume:

Issue:

Issue 3

Year:

2024

Pages:

101-110

Abstract

Real-time digital signal processing (DSP) increasingly demands high throughput, deterministic latency, and energy-efficient execution—requirements that conventional FPGA designs often fail to meet due to memory-access bottlenecks rather than computational limitations. This paper presents a Memory-Aware Architecture Optimization Framework designed to maximize real-time DSP performance by restructuring the memory hierarchy and aligning it with high-speed computation pipelines. The proposed framework integrates multi-banked BRAM/URAM partitioning, sliding-window and tiled buffering for data reuse, pipeline-aligned memory layout transformation, and conflict-free parallel access scheduling. Implemented on a Xilinx Zynq-7020 FPGA, the architecture significantly reduces off-chip DDR traffic and ensures continuous data availability to DSP compute units. Experimental results demonstrate up to 38% reduction in latency, 1.6×–1.9× increase in throughput, 27% lower dynamic power consumption, and up to 22% savings in FPGA resources compared to a baseline design. These findings highlight that optimizing data movement—not computation—plays the dominant role in achieving high-speed, real-time performance on modern FPGA platforms and is essential for next-generation signal processing applications in communication systems, radar imaging, biomedical instrumentation, and edge intelligence.

Keywords

FPGA, Real-Time Signal Processing, Memory-Aware Optimization, Multi-Banked BRAM, Sliding-Window Buffering, Memory Tiling, Pipeline Alignment, DDR Minimization, High-Throughput DSP, Reconfigurable Computing.

References

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DOI: https://doi.org/10.64971/j.cph.ijsdip.v12.i3.1.2024